Stronger Google CPU ramp, and upside optionality in Google ASICs; Upgrade to OW

Research evidence excerpt

Stronger Google CPU ramp, and upside optionality in Google ASICs; Upgrade to OW

Gokul Hariharan AC Asia Pacific Equity Research

(852) 2800-8564 02 August 2026 J P M O R G A N

gokul.hariharan@jpmorgan.com

several versions and engagement models that are currently discussed as part of the RFQ

process. We believe that the primary version is still a semi-CoT approach (similar to

TPUv8t or v9 Humufish), where Google in-house design team works on the Compute die

design, while Mediatek provides Serdes, Die-2-Die IP, packaging design and overall

integration and Foundry support. At the same time, there appear to be other projects with

various engagement models, which involve (1) The back-end design of the Compute die

being outsourced to pure design service vendors such as GUC or Alchip in a TK3 model;

(2) Only IP being sourced by Google separately, while allocating pieces of the design

service work for various fabless and design service vendors, with Foundry procurement

being handled directly by Google, similar to the Amazon Trainium approach. Overall, we

believe that through the evolution from TPUv8 to v10 families, the black-box model from

US fabless vendor (where IP, design service, manufacturing and packaging value add are

all bundled together at high margins) will be broken down systematically in favor of a

disaggregated approach. The highest value capture from this approach in the next 3-4

years is likely to accrue to Mediatek (primary source of TPUv10, with increasing value

in every generation from v8 to v10), while design service vendors such as GUC and

Alchip could also benefit somewhat, depending on whether Google is able to embrace a

full-scale CoT approach. For non-TPU projects, the opportunity for a full-COT approach