China AI chip: Key takeaways from WAIC 2026: China‘s AI infrastructure shifts

Research evidence excerpt

China AI chip: Key takeaways from WAIC 2026: China‘s AI infrastructure shifts

Asia Pacific Equity Research

20 July 2026

China AI chip

Key takeaways from WAIC 2026: China's AI

infrastructure shifts

Following our two-day visit to WAIC 2026, we believe China’s AI Technology

infrastructure ecosystem has demonstrated a decisive shift from single- AC Billy Feng

chip benchmarking to system-level deployment, and from capacity build- (86-21) 6106 6359

out to a genuine token economy. Our key takeaways are: 1) delivering billy.feng@jpmorgan.com

single-chip performance at effective Hopper-class level has become the SAC Registration Number: S1730520030005

baseline, while Prefill/Decode-disaggregation architectures have moved Ri Xu

from experimental to standard; 2) super-node solutions spanning dozens to (86-21) 6106 6318

ri.xu@jpmchase.com

thousands of cards have emerged as the critical system-level answer to SAC Registration Number: S1730522100001

process-node constraints, explicitly targeting trillion-parameter model J.P. Morgan Securities (China) Company

deployment; and 3) making AI compute affordable and ubiquitous is the Limited

driving force, but deployment requires sustained ecosystem co-innovation.

Our top picks within the ramping indigenous AI supply chain are Iluvatar

CoreX, JCET, NAURA, and AMEC.

• The baseline of chip performance has reset to Hopper-class. Even

though domestic AI chip vendors remain focused on solving near-term

capacity and supply bottlenecks, we believe the next imperative is

delivering effective Hopper-class compute by late this year and into

2027. For instance, Iluvatar CoreX launched its Tiangai 300 chip, which

claims 10-20% superior performance versus Hopper architecture on

selective inference metrics. The PD-disaggregation paradigm has become