Asia AI Semi & Server

Research evidence excerpt

Asia AI Semi & Server

s. As such, we would still be buyers into weakness. We raise target prices

for nine AI tech companies (mentioned below) with this Anchor Report.

TSMC turning aggressive on CoW plan, but the bottleneck could shift to WoS

We now expect TSMC to “target” chip-on-wafer-on-substrate (CoWoS) capacity of

2,000kpcs in 2027F, from 1,100kpcs in 2026F, and forecast that it would need 2,500-

3,500kpcs of CoWoS output by 2029F, depending on the scale of annual price hikes, to

achieve its “high-50%” AI revenue CAGR over 2024-29E. In addition, if Feynman production

fully migrates to chip-on-panel-on-substrate (CoPoS) in 2029F, TSMC would need to build

700-800kpcs CoPoS capacity by 2029F. However, our contrarian view is that “WoS” and

many other small components would very likely become a bigger bottleneck than “CoW” in

the remaining of 2026F and also into 2027F – which is not a bad reading for long-term cycle

sustainability, in our view, but would likely drive short-term share price volatility. As such, we

only “model” 1,800kpcs of CoWoS output in 2028F – which would have profound

implications for different GPU/ASIC vendors in 2027F, i.e. when the elephants (nVidia

[NVDA US, Not rated] and Google [GOOGL US, Not rated]) fight, the grass (other

xPU/ASIC) would get trampled, we think. Separately, outsourced semiconductor assembly

and test (OSAT) vendors would not only benefit from TSMC’s growing WoS outsourcing but

also from further price hikes (given ongoing material cost inflation) and upside from their

own CoWoS-like full process (driven by CPUs).

SoIC and CoPoS to counter EMIB-T; relevant supply chains to benefit

Intel’s (INTC US, Not rated) embedded multi-die interconnect bridge with TSV (EMIB-T)