ASE Technology Holding Co Ltd Key takeaways from JPM APAC All Stars London Conference

Research evidence excerpt

ASE Technology Holding Co Ltd Key takeaways from JPM APAC All Stars London Conference

Gokul Hariharan AC Asia Pacific Equity Research

(852) 2800-8564 30 June 2026 J P M O R G A N

gokul.hariharan@jpmorgan.com

challenges pose imminent ramping risk: Intel EMIB has seen more interest from

Fabless vendors recently, given tight CoWoS supply and diversification needs for major

ASIC projects (such as MediaTek’s TPU v9). ASE expressed less worry about the

emerging competition and mentioned that it also has the capability to provide similar

solutions with bridge dies embedded in substrates. In addition, we believe that CTE

(Coefficient of Thermal Expansion) mismatch between substrate and silicon bridge and

yield management (based on our checks, yields are only around 60% for 9–10x reticle-

size configurations with 25+ EMIB bridge dies) remain key challenges for embedded

substrate based packages. We anticipate ASE’s competitive edge to stay intact in non-

TSMC CoWoS-like solutions (well-positioned in smaller size packages, such as CPUs),

given its close partnership with TSMC and satisfactory yields ready for mass production.

On a different note, ASE appears less concerned about China’s competition (despite

~10% China exposure for ATM), given decent performance in its China business in 2026

and limited customer overlap with Chinese peers, who focus more on domestic AI chip

projects.

• CPO and Panel-level packaging as a long-term growth driver: ASE indicated that the

company should see small revenue from CPO in 2026, with a more meaningful ramp in

2027. While a mass production timeline remains uncertain, ASE believes it has been well

positioned and should play a part in the CPO supply chain (we believe downstream

packaging and testing steps for the COUPE process).