Meta Vistara CXL ASIC - Validating the Case for CXL (Driving 25% Server Reduction; Confidence in CXL w/ 100TB+ Model Sizes)

Research evidence excerpt

Meta Vistara CXL ASIC - Validating the Case for CXL (Driving 25% Server Reduction; Confidence in CXL w/ 100TB+ Model Sizes)

Meta Vistara CXL ASIC - Validating the Case for CXL (Driving 25% Server Reduction; Confidence in CXL w/ 100TB+ Model Equity ResearchSizes)

HW + Software Co-design & Engineering Key CXL Enablers. Meta outlines the key debate against

CXL (high tail latency, low bandwidth + high latency, and high runtime overhead with added memory

layers) which it believes it has solved with hardware + software co-design & thoughtful engineering.

Meta also highlighted the challenge in recycling DDR4 for CXL expansion, which Vistara has solved,

as prior CXL solutions are not supportive of reusing older memory (majority of CXL solutions bundle

DRAM + Controller, preventing DIMM reuse; DDR4 support not available).

Additional Quick Notes

• Meta cited the majority of workloads as memory capacity bound rather than bandwidth bound,

with >40% of Meta's millions of CPU servers memory capacity bound.

• Memory & server useful life mismatch (~7-10 years vs.~3-5 years) drives DRAM DIMMs to be

wasted in early retirement.

• Limited DRAM capacity has traditionally led write operations to be predominantly absorbed

by SSDs, now CXL solutions can help absorb a greater proportion of writes to memory, driving

SSD useful life expansion. Meta also noted that fewer cache misses (key value cache is outside of

memory window) result in less requests moving to flash and remote storage tiers, driving cost

savings w/ minimized need for overprovisioning and reduced network bandwidth consumption.

• DRAM DIMMs also noted at 69% of its emissions of its CPU server fleet.

Source: Vistara: Making CXL Real—Full Path from ASIC Design and OS Support to Hyperscale Deployment

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