IT HARDWARE : Huawei's Tau-Scaling - Read-x

研报英文原文证据摘录

IT HARDWARE : Huawei's Tau-Scaling - Read-x

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IT HARDWARE

Huawei's Tau-Scaling - Read-x

Huawei showed their “Tau-Scaling Law” at ICAS 2026 yesterday, proposing a shift from measuring26 MAY 2026

Securities Research Report transistor scaling geometrically i.e. transistors per unit area (density) – Moore’s Law, to temporal

Production time: 10:51* (London time)

scaling, where signal processing time (latency) is key. Underlying this law is a reliance on

Research Analysts & Publishing Entities

advanced 3D-packaging (+ve Besi), a function of export control restrictions.

Jakob Bluestone, CFA

BNP Paribas London Branch LogicFolding is their newest advanced packaging – impressive on paper(+44) 203 430 8468

Jakob.Bluestone@uk.bnpparibas.com Huawei’s Tau-Scaling combines on transistor, circuit, chip and system level. “LogicFolding”

addresses the circuit. Traditional logic stacking (e.g. AMD V-Cache) is die-to-die (see figure 2

Martin Jungfleisch

overleaf), Huawei claim macro-to-macro, a deeper level with a sub-2µm pitch (HBI) which is muchBNP Paribas SA

(+49) 69 4272 97328 finer than TSMC’s leading edge at 6µm. The company claims this unlocks increased clock

martin.jungfleisch@bnpparibas.com frequency (latency scaling), unlike in die-to-die bonding. We note that Besi (+) is unrestricted on

Kohulan Paramaguru, CFA hybrid bonder shipments to China.

BNP Paribas London Branch

(+44) 203 430 8546 Transistor density claims are marketing, the move to packaging suggests more DUV needed

kohulan.paramaguru@uk.bnpparibas.com

By stacking chips in 3D, the density per unit area (2D) increases, this facilitates claimed jumps in

density. The underlying process technology (DUV multi-patterning) seems unchanged. The jump in