Semiconductor Testing

Research evidence excerpt

Semiconductor Testing

Macquarie Equity Research Semiconductor Testing

Executive summary

Testing is evolving from through-put driven volume to complexity-led value. The

semiconductor testing industry is undergoing a fundamental structural shift. For two

decades, testing was a volume-based back-end cost centre focused on throughput (ie,

testing as many chips as possible), as quickly as possible). Today, the AI-driven explosion in

chip complexity, advanced packaging, and soaring chip ASPs has transformed testing into

a critical yield-insurance mandate. We believe the market is entering a multi-year testing

super cycle in which test content value is decoupling from unit growth, driving a significant

TAM expansion for equipment and interface suppliers. The following key factors support this

thesis:

• Complex architectures require more testing. AI chips often use heterogeneous

integration (chiplets and multi-die packages), which means each component must be

tested individually and in the integrated package (see details in our thematic report,

Beyond Moore's Law [13 November 2024]). The transition from monolithic designs to

multi-die/chiplet architectures has exponentially increased the points of failure per

package. In the era of 2.5D/3D packaging, the cost of a test escape (ie, allowing a faulty

die into a final assembly) is catastrophic. Multiple testing steps are inserted into the

standard testing flow (ie, insertions) ensure that both the standalone dies and the

combined system meet yield standard. For example, a CPU+GPU chiplet package will

undergo wafer sort on each die, then an interposer-level test, and finally a system-level

test (SLT) of the entire module, adding new test insertion points that didn’t exist before.